“With RISC, a central processing unit (CPU) implements the processor design principle of simplified instructions that can do less but can execute more rapidly.”
None of this is to say RISC or by extension ARM is bad, just that where everything currently is it’s not a good choice for everyday computing. By design its as light weight and simple as possible so that it can perform its specific function faster and more efficiently with less overhead than a more general purpose processor.
Just to add - a rather large reason the technology we have today even exists is thanks in no small part to the x86 architecture and it’s immense backwards-compatibility.
The Fujitsu A64FX had full 512-bit SVE, with 2x 512-bit units per core and HBM memory, which is as CISC as it gets. IIRC was the “widest” CPU that could get the most done per clock, at the time, and the US Department of Energy seemed to love them.
And then you have tiny cores like Intel’s in order ones that are way thinner than ARM designs.
Reality is decoding doesn’t take up much die space these days and stuff is decoded into micro ops anyway. The ISA has an effect, but efficiency/appropriateness for different platforms comes down to design and business decisions more than the ISA.
It’s not though, ARM themselves admit it. https://www.arm.com/glossary/risc.
“With RISC, a central processing unit (CPU) implements the processor design principle of simplified instructions that can do less but can execute more rapidly.”
None of this is to say RISC or by extension ARM is bad, just that where everything currently is it’s not a good choice for everyday computing. By design its as light weight and simple as possible so that it can perform its specific function faster and more efficiently with less overhead than a more general purpose processor.
Geeks for geeks has a good writeup on it.
https://www.geeksforgeeks.org/computer-organization-risc-and-cisc/
Just to add - a rather large reason the technology we have today even exists is thanks in no small part to the x86 architecture and it’s immense backwards-compatibility.
I mean, that doesn’t mean much.
The Fujitsu A64FX had full 512-bit SVE, with 2x 512-bit units per core and HBM memory, which is as CISC as it gets. IIRC was the “widest” CPU that could get the most done per clock, at the time, and the US Department of Energy seemed to love them.
And then you have tiny cores like Intel’s in order ones that are way thinner than ARM designs.
Reality is decoding doesn’t take up much die space these days and stuff is decoded into micro ops anyway. The ISA has an effect, but efficiency/appropriateness for different platforms comes down to design and business decisions more than the ISA.